Applications

The CEVERO Project aims at developing Chip multi-procEssors for Very Energy-efficient aeRospace missiOns. Given the nature of their operation, aerospace and mission-critical system processors are customarily required to be fault-tolerant and energy-efficient. Fault tolerance is required to deal with the higher probability of radiation strikes when operating far from the Earth’s surface, which causes failure due to “single event upsets” (SEUs) and “single event latchups” (SELs). Nowadays, these processors are even more susceptible to such events because of smaller transistor sizes and lower supply voltages featured in modern semiconductor technology. The energy efficiency requirement arises from power and cooling constraints. In space, there is no air to help dissipate heat. As a result, the heat generated by the system has to be limited. More power, besides producing more heat, implies in higher financial costs with larger solar panels, larger batteries, and consequently more weight and volume to be launched into space. In this project, we propose to design a flexible fault-tolerant multi-core processor based on a leading-edge RISC-V platform to be used in aerospace and mission-critical applications such as the Brazilian nanosatellite network for environmental data collection. Multi-core systems have been widely used as a way to achieve superior performance without an exponential increase in power consumption. The proposed design uses the inherent core-level redundancy of these systems to deliver fault tolerance. Additionally, considering that not all parts of a given aerospace application need to be fault-tolerant, e.g. those inherently corrupted by signal noise, the proposed design can switch to an unsafe mode to double or triple its available parallel performance. We aim to enable systems that can deliver higher performance and higher energy efficiency in uncertainty-driven computations and yet be able to switch to a fault-tolerant mode for critical computations, according to the application’s dynamic demand.

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